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[Bug 1001068] New: Bug in serial driver when using Parity (Even orOdd)


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           Summary: Bug in serial driver when using Parity (Even or Odd)
           Product: eCos
           Version: 3.0
          Platform: stm32e_eval (ST STM3210E EVAL board)
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: normal
          Priority: low
         Component: Serial
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: pme.neratec@gmx.ch
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


stm32_serial.h defines the following "translation" (see
http://ecos.sourceware.org/cgi-bin/cvsweb.cgi/ecos/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h?rev=1.2&content-type=text/x-cvsweb-markup&cvsroot=ecos):

// Translate system parity selector into local values.
static cyg_uint32 select_parity[] = {
    0,                                                                  // No
parity
    CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_EVEN,    // Even
parity
    CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_ODD,     // Odd
parity
    0,  // Mark (1) parity -- not supported
    0  // Space (0) parity -- not supported
};


But - when selecting a parity (EVEN or ODD), you must also configure the M9-Bit
on the stm32. If you don't, you end up sending 7 databits and 1 parity bit
(instead of sending 8 databits and 1 parity bit).

Therefore the correct "translation" array must look like this:
// Translate system parity selector into local values.
static cyg_uint32 select_parity[] = {
    0,                                                                  // No
parity
   
CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_EVEN|CYGHWR_HAL_STM32_UART_CR1_M_9,
   // Even parity
   
CYGHWR_HAL_STM32_UART_CR1_PCE|CYGHWR_HAL_STM32_UART_CR1_PS_ODD|CYGHWR_HAL_STM32_UART_CR1_M_9,
    // Odd parity
    0,  // Mark (1) parity -- not supported
    0  // Space (0) parity -- not supported
};

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