This is the mail archive of the ecos-bugs@sourceware.org mailing list for the eCos project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[Bug 1001111] Access to saved registers from Cortex-M ISR


Please do not reply to this email. Use the web interface provided at:
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001111

Nick Garnett <nickg@ecoscentric.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |nickg@ecoscentric.com

--- Comment #1 from Nick Garnett <nickg@ecoscentric.com> 2011-01-07 13:39:06 GMT ---
The intention with the code as it was written is that if anything needs access
to the interrupt state then it should enable the existing code that saves a
full and complete CPU state and stores it in hal_saved_interrupt_state; either
by defining the CTRLC support option or by new means. Interested code can then
fetch it from there. That way this code is only included when this
functionality is required. The extra ISR argument is also a bad idea, it has
caused problems in other architectures and my intention was to keep the
Cortex-M architecture clean and not have it.

There is maybe a case for defining a CDL option that controls this piece of
code and have that depend on CTRLC and BREAK support, as well as allowing it to
be enabled by any other package.

-- 
Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are the assignee for the bug.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]