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[Bug 1001114] New: New port: NXP LPC17XX Variant, OlimexLPC-1766-STK platform


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           Summary: New port: NXP LPC17XX Variant, Olimex LPC-1766-STK
                    platform
           Product: eCos
           Version: CVS
          Platform: Other (please specify)
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: low
         Component: HAL
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: ilijak@siva.com.mk
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


Created an attachment (id=1077)
 --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1077)
LPC17xx HAL. Extract in packages/hal.

This is an eCos port to NXP LPC17xx Cortex-M controller family. Following
packages are submitted:
    Variant: LPC17XX
    Platform Olimex LPC-1766-STK.

Specific issues:

1. Cortex-M architecture
Due to LPC17XX specific SRAM location, a change of Vector Table location is
necessary which requires change in Cortex-M architecture hal_io.h header. Also,
due to different understanding of clock sources (int vs ext) between different
chip vendors, some changes in SysTick clock source selection macros are
necessary. All architectural patches are submitted in a separate bug referenced
below.

2. Device drivers
LPC17xx peripherals are compatible with LPC24xx so we can reuse drivers with
minor adjustments such as device base addresses. LPC24xx UART, Ethernet and
Wallclock drivers have been prepared in order to work on both old (LPC24xx) and
new (LPC17XX) platforms. Since the changes also affect LPC24xx (although
changes retain backward compatibility with LPC24XX) the driver patches are
submitted in a separate bug referenced below.

3. lwIP and LPC17xx AHB memory block(s)

lwIP makes use of statically allocated memory for buffers and heap (objects
defined as global static variables). LPC17XX, on the other hand, contains one
or two AHB memory blocks (16 KiB each) intended for "peripheral use". In order
to utilize this memory for lwIP usage:
    - a new memory section ahb_bss is defined
(include/pkgconf/mlt_cortexm_lpc17xx_inc.ldi);
    - CDL component "LPC17xx specific memory option" is submitted to lwIP
memory options by LPC-1766-STK CDL;
    - lwIP is patched to use special section if one is defined. lwIP patches
are submitted in a separate bug referenced below.

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