[Bug 1001117] New: Cortex-M architecture fixes.

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           Summary: Cortex-M architecture fixes.
           Product: eCos
           Version: CVS
          Platform: Other (please specify)
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: low
         Component: HAL
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: ilijak@siva.com.mk
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


Created an attachment (id=1083)
 --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1083)
VTOR and SysTick fixes for override.

In current Cortex-M architecture port some macros are defined in architecture
headers without possibility for overriding by variant and/or platform.

1. Vector Table Offset Register - VTOR

CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM places VTOR at beginning of SRAM 0x20000000
following ARM guides. However, already there are devices with no memoru at this
address such as LPC17XX BUG #1001114

Solution: Conditional define of CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM that allows
for override.

2. SysTick

SysTick setting uses exclusively external clock. Definition ext. vs int. seem
to be the chip vendor/designer "prerogative" so we need flexibility.
Also the definitions of CYGARC_REG_SYSTICK_CSR_CLK_EXT and
CYGARC_REG_SYSTICK_CSR_CLK_INT seem too complicated.

Solution: New macro CYGARC_REG_SYSTICK_CSR_CLK_SRC and CDL for SysTick clock
source selection. CYGARC_REG_SYSTICK_CSR_CLK_EXT and
CYGARC_REG_SYSTICK_CSR_CLK_INT defines made explicit.

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