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[Bug 1001090] Added option to run system timer with internal clock


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Ilija Kocho <ilijak@siva.com.mk> changed:

           What    |Removed                     |Added
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                 CC|                            |ilijak@siva.com.mk

--- Comment #3 from Ilija Kocho <ilijak@siva.com.mk> 2011-01-16 17:08:10 GMT ---
(In reply to comment #2)
> CYGSEM_HAL_SYSTICK_CLK_INTERNAL is a CDL option to be defined in the variant
> configuration. Is that ok or shall it be defined in the cortexm CDL?

I downloaded your parch and produced a CDL bool option into LPC17xx port ( Bug
1001114 ). Needles to say, works fine. Of course there is (always) a question
of flavor: a bool as is now or data - CDL defines CYGARC_REG_SYSTICK_CLK_SRC as
a choice between Int/Ext (no need for CYGSEM_HAL_SYSTICK_CLK_INTERNAL ).

Regarding your question: IMO this bit is a part of the Cortex-M architecture
and it would be good if Cortex-M architecture CDL reflects it.

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