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[Bug 1001606] Enable the cache on Kinetis in RAM startup mode
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: ecos-bugs at ecos dot sourceware dot org
- Date: Mon, 11 Jun 2012 23:37:59 +0100
- Subject: [Bug 1001606] Enable the cache on Kinetis in RAM startup mode
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- References: <bug-1001606-13@http.bugs.ecos.sourceware.org/>
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--- Comment #8 from Ilija Kocho <ilijak@siva.com.mk> 2012-06-11 23:37:54 BST ---
Jifl
Here are considerations on your comment #6 that I have left out in comment #7.
(In reply to comment #5)
[snip]
> Not related to the particular patch, but still to do with caching
> configuration... Some subsystems have their caching configuration set under
> CYGPKG_HAL_KINETIS_CACHE, whereas others have them set in their own tree - or
> at least SDRAM/DDR does, but I haven't looked more widely for others. And the
> two key interfaces CYGINT_HAL_CACHE and CYGINT_HAL_HAS_NONCACHEABLE live under
> a separate component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES. I think related
> options ought to be kept in the same place. OR if there's a good reason why
> not, a note should be placed in the description e.g. of
I wander how have they landed here. They should appear just before (or
CYGINT_HAL_HAS_NONCACHEABLE might be parented by) CYGPKG_HAL_KINETIS_CACHE.
> CYGPKG_HAL_KINETIS_CACHE pointing users in the right direction of other
> cache-related configuration options. In line with my thoughts at the top, I
> think the two interfaces could be brought under CYGPKG_HAL_KINETIS_CACHE which
> would then become "flavor none/no_define", with the active_if then applying to
> CYGHWR_HAL_NON_CACHABLE. hal_cortexm_kinetis_conf_cache_regions() can be called
> from HAL_DCACHE_ENABLE() and HAL_ICACHE_ENABLE() appropriately, so it's still
> only called if actually needed (and linker garbage collection will remove it if
> never called).
>
With the change above I would like to keep CYGPKG_HAL_KINETIS_CACHE as is. As I
noted in comment #7, the cache is optional on Kinetis - therefore it's absence
is more intuitive presented if it's grayed for cache-less parts.
[snip]
>
> - The descriptions of options like CYGHWR_HAL_ENET_TCD_SECTION appear to
> conflict with their default settings.
>
I guess you refer to sram being brought in conjunction with the cache. But SRAM
is non-cachable (always) and that's stated in K70 manual (Table 3-41. Cache
regions). I guess it wouldn't be strange to K70 users.
Ilija
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