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[Bug 1001639] New: Problems with i2c.cxx
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: ecos-bugs at ecos dot sourceware dot org
- Date: Tue, 31 Jul 2012 09:40:21 +0100
- Subject: [Bug 1001639] New: Problems with i2c.cxx
- Auto-submitted: auto-generated
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Summary: Problems with i2c.cxx
Class: Advice Request
Created an attachment (id=1852)
proposed patch to fix this defect
There are several problems in the i2c bit-banging base class.
1. The phase position of output data is incorrect.
When the SDA bit is written, the SCL rises immediately afterwards.
The possbibly different rise times of both signals crate a race condition,
because the I2C slave needs to sample the SDA at the rising edge of SCL.
2. The clock stretching is needed for all data transfers, even the stop bit.
There have been problems due to missing bit-stretching
with SFP Compatible Fiber Optical Transceivers.
3. NAK of the last sent byte is ignored.
4. In the case of a I2C bus multiplexer device, the assertins
in cyg_i2c_transaction_xxx are too rigorous.
If the I2C Memory is not directly connected, but thru a PCA9547 I2C bus
multiplexer, we have to instruct the PCA9547 to switch the I2C Bus,
before the I2C Memory can be accessed.
Of course the whole process should be a I2C transaction, but the assertions
in cyg_i2c_transaction_xxx force all communication only to one slave at a time.
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