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[Bug 1001456] HAL misses Interrupt Clear-Pending Registers handling:wasted processing power
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: ecos-bugs at ecos dot sourceware dot org
- Date: Thu, 27 Sep 2012 09:52:41 +0100
- Subject: [Bug 1001456] HAL misses Interrupt Clear-Pending Registers handling:wasted processing power
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--- Comment #26 from Bernard FouchÃ <firstname.lastname@example.org> 2012-09-27 09:52:36 BST ---
(In reply to comment #25)
> But I wouldn't overstate the problem, as far I can tell this will only happen
> with certain designs of devices, and only then if certain situations combine,
> which therefore makes it uncommon. That's not to say it's irrelevant, but it's
> not like it happens every interrupt or anything like that.
If you're not looking for this problem, you won't see it :-).
For instance you send X KB of data in a FIFO based driver (say the UART) and
you don't count the number of times the ISR/DSR sequence is triggered but just
check that the UART traffic is correctly sent: everything seems fine since the
job is done.
But if you start counting ISR/DSR then you wonder why you have a number of
ISR/DSR that is bigger, sometimes much much bigger, that the number of bytes
you sent (or have received) while with a FIFO you should have a lower number of
ISR/DSR compared to the number of bytes sent/received(otherwise the interest of
the FIFO is questionable).
This is how I ran into this issue, first with the UART driver then I found it
with the other drivers I considered (SSP, CAN).
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