[Bug 1001606] Enable the cache on Kinetis in RAM startup mode

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--- Comment #18 from Ilija Kocho <ilijak@siva.com.mk> 2012-09-28 16:59:26 BST ---
Created an attachment (id=1945)
 --> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1945)
Cache and DDRAM fixes/improvements 120928

(In reply to comment #5)

Hi Jifl

Here I attach a patch with some fixes that I have announced in my previous
posts. In addition to addressing your remarks that I have accepted in comment
#7 I have added some fixes to DDRAM configuration. Main improvements are PAD
control, and slight memory optimization of initialization code for DDRAM.

> Hi Ilija,
> 
> Looking at this patch, I decided to look a bit closer at the Kinetis. Some
> things to do with caches strike me as a bit unusual, but hopefully you can
> clarify where my misunderstandings lie:
> 
[ snip - discussed in previous replies]

> 
> Not related to the particular patch, but still to do with caching
> configuration... Some subsystems have their caching configuration set under
> CYGPKG_HAL_KINETIS_CACHE, whereas others have them set in their own tree - or
> at least SDRAM/DDR does, but I haven't looked more widely for others. And the
> two key interfaces CYGINT_HAL_CACHE and CYGINT_HAL_HAS_NONCACHEABLE live under
> a separate component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES. 

Now they are moved out of CYGHWR_HAL_KINETIS_MEMORY_RESOURCES.

>I think related
> options ought to be kept in the same place. OR if there's a good reason why
> not, a note should be placed in the description e.g. of
> CYGPKG_HAL_KINETIS_CACHE pointing users in the right direction of other
> cache-related configuration options.

I assume you are referring to CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB and
similar options. They are DDRAM rather than cache configuration options. But
you are right, some explanation is good idea so I wrote explanatory
descriptions for CDLs under DDRAM. Also I grouped "cachable" and "non-cachable"
options so now DDRAM CDL should look simple and more compact.

[snipped - replied earlier in other comments]

> 
> - Incidentally some of the indentation in the kinetis CDL is a bit off, 
> e.g. underneath CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE, at the end of
> CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS and beginning of
> CYGHWR_HAL_KINETIS_FLASH_CONF.

Reformatted.



The attached evolution patch does not affect (and should not be affected by)
our eventual change of cache treatment (separate / unified). I have tested the
code on K60 and K70, and I would like to commit it if you don't have
objections.

Ilija

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