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[Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: unassigned at bugs dot ecos dot sourceware dot org
- Date: Mon, 15 Apr 2013 22:29:36 +0000
- Subject: [Bug 1001815] Freescale DSPI avoid Rx DMA if transfer fits in FIFO.
- Auto-submitted: auto-generated
- References: <bug-1001815-777 at http dot bugs dot ecos dot sourceware dot org/>
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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815
Bug 1001815 depends on bug 1001814, which changed state.
Bug 1001814 Summary: Kinetis clock gating
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001814
What |Removed |Added
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Status|NEW |RESOLVED
Resolution|--- |CURRENTRELEASE
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