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[Bug 1001837] Rich FlexBus RAM layout
- From: bugzilla-daemon at bugs dot ecos dot sourceware dot org
- To: unassigned at bugs dot ecos dot sourceware dot org
- Date: Fri, 03 May 2013 17:48:35 +0000
- Subject: [Bug 1001837] Rich FlexBus RAM layout
- Auto-submitted: auto-generated
- References: <bug-1001837-777 at http dot bugs dot ecos dot sourceware dot org/>
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--- Comment #12 from Ilija Kocho <email@example.com> ---
(In reply to comment #7)
> I assume from Ilija's comments that DMA bypasses the cache, hence the need
> to invalidate it.
> I assume the TCD limitation is because the eDMA logic in the device is
> connected tightly with the memory bus logic and can't route through the
> cache, similar to how DMA works directly on memory without the cache.
eDMA has no access to cache, but the problem could be (also) solved with cache
synchronisation/invalidation. However, it would require extra CPU time and
since TCD typically occupy little memory (even cumulative), for best
performance I have chosen to put them in SRAM [by default].
Same discussion applies to Ethernet buffer descriptors.
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