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[Bug 1002169] Broken cyg_interrupt_disable/enable for cortex m3


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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1002169

--- Comment #1 from Bernard Fouché <bernard.fouche@kuantic.com> ---
It appears that priority levels in SHPR.. must also be shifted, as one can see
in CMSIS code. For instance, line 565 of listing shown at
https://developer.mbed.org/users/screamer/code/mbed/docs/aff670d0d510/core__cm0_8h_source.html
:

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