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[Bug 1002169] Broken cyg_interrupt_disable/enable for cortex m3


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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1002169

Nick Garnett <nickg@ecoscentric.com> changed:

           What    |Removed                     |Added
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                 CC|                            |nickg@ecoscentric.com

--- Comment #5 from Nick Garnett <nickg@ecoscentric.com> ---
Bernard,

I think you have misunderstood how the priority mechanism in the Cortex-M, and
therefore in eCos, is intended to work. The priority is an 8 bit value that
maps on to the hardware priorities by ignoring some lower bits of the value.
ARM designed it this way so that portable code always uses 8 bit values,
regardless of the number of priorities implemented by any particular CPU. There
is no need to do any shifting to match the implemented priority levels, the
hardware handles the mapping. This is why the implemented bits are at the top
of the registers rather than the bottom.

Users cannot set a priority value less than CYGNUM_HAL_CORTEXM_PRIORITY_MAX
since they are always offset by that value. The only vectors with a priority of
zero are the exception vectors, so they can be raised even in
interrupt-disabled code.

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