//
// CTS electronics srl	(www.ctsgroup.it)
// Corso Vercelli, 332 - 10015 Ivrea (TORINO) Italy
// All rights reserved
//
//             Creato il: 4 Ottobre, 2004
//       Ultima modifica: 26 Ottobre, 2004
//
//              Progetto: dispensatore monete
//
//                Autore: Marco SICHERI
//                        (m.sicheri@ctsgroup.it)
//
//
// Made in Italy
//
//-----------------------------------------------------------------------------
//
// NOTE: only fo Samsung s3c44b0x
//
//-----------------------------------------------------------------------------


#include "ctsinc.h"
#include "../../repository/packages/hal/arm/b2/v2_0/include/hal_setting.h"

extern WORD *PDATF;


////////////////////////////////////////////////////////////////////////////////
// Prototipi
////////////////////////////////////////////////////////////////////////////////
void intTimer2dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
cyg_uint32 intTimer2isr(cyg_vector_t vector, cyg_addrword_t data);


////////////////////////////////////////////////////////////////////////////////
// CPU Timer Register
////////////////////////////////////////////////////////////////////////////////
WORD *TCON = (WORD *)0x1d50008;		//Timer Control Register
WORD *TCNTB2 = (WORD *)0x01d50024;	//T2 Count Buffer Register
WORD *TCMPB2 = (WORD *)0x01d50028;	//T2 Compare Buffer Register
WORD *TCNTO2 = (WORD *)0x01d5002c;	//T2 Count Observation Register


////////////////////////////////////////////////////////////////////////////////
// CPU Interupt 
////////////////////////////////////////////////////////////////////////////////
WORD *INTMOD = (WORD *)0x01e00008;	//Interrupt Mode Register
WORD *INTMSK = (WORD *)0x01e0000C;	//Interrupt Mask Register
WORD *I_ISPC = (WORD *)0x01E00024;	//IRQ interrupt service pending clear register


////////////////////////////////////////////////////////////////////////////////
// IRQ PRIORITY 
////////////////////////////////////////////////////////////////////////////////
WORD *I_PSLV = (WORD *)0x01E00010;	//IRQ PRIORITY OF SLAVE REGISTER bit 11 e 10 per t2
WORD *I_PMST = (WORD *)0x01E00014;	//IRQ PRIORITY OF MASTER REGISTER bit 11 e 10 per t2


////////////////////////////////////////////////////////////////////////////////
// Gestione Interrupt Timer2
////////////////////////////////////////////////////////////////////////////////
cyg_handle_t intTimer2Handle;
cyg_interrupt intTimer2;
cyg_sem_t data_ready;


//
// ----- CTSTIMERInit -------------------------------------------
//
BYTE CTSTIMERInit(void)
{
	//
	// Impostazione routine di Interrupt per Timer2
	//
	cyg_semaphore_init(&data_ready, 0);
	cyg_interrupt_create(
				11,
				0,
				0,
				&intTimer2isr,
				&intTimer2dsr,
				&intTimer2Handle,
				&intTimer2);
	//Attach the interupt to the vector
	cyg_interrupt_attach(intTimer2Handle);
	cyg_interrupt_unmask(intTimer2Handle);

	return (CPSRC_OK);
}

//
// ----- CTSTIMERTimer2Start -------------------------------------------
//
void CTSTIMERTimer2Start(HWORD periodo, BOOL outSignal)
//
// La routine dic attura IRQ č in packages/hal/arm/b2/v2_0/src/b2_misc.c
//
{
	WORD value;

	//Stop
	(*TCON) &= ~BIT12;	

	//Mask Timer 2
	(*INTMSK) |= BIT11;

	//
	// Programmazione Timer 2 per motore Step
	//
	(*TCNTB2) = periodo;	//Periodo
	(*TCMPB2) = 0;			//compare value

	if (outSignal == TRUE)
	{
		//CPU timer2 out toggle
		WORD *PCONE = (WORD *)0x01D20028;	//Port E Control
		*PCONE |= BIT11;
		*PCONE &= ~BIT10;
	}

	//Set T2 Interrupt Mode
	(*INTMOD) &= ~BIT11;	// = IRQ

	//Unmask Timer 2
	(*INTMSK) &= ~BIT11;

	//Set Priority
//	(*I_PSLV) &= ~(BIT11 | BIT10); //se la tocco non funziona pių
//	(*I_PMST) &= ~(BIT11 | BIT10);

	//
	// NOTE: deve essere questa la sequenza, altrimenti non funziona....
	//

	//Set T2 mode
	value = (*TCON);
	value |= BIT15;		//Autoreload	ON
	value &= ~BIT14;	//inverter		OFF
	value |= BIT13;		//Update cnt	ON
	(*TCON) = value;

	value = (*TCON);
	value &= ~(BIT12 | BIT13 | BIT14 | BIT15);	
	value |= (BIT12 | BIT15);	//Start + Autoreload
	(*TCON) = value;	//Start + Autoreload
}

//
// ----- CTSTIMERBreakTimer2 -------------------------------------------
//
void CTSTIMERTimer2Stop(void)
{
	(*TCON) &= ~BIT12;	//Stop

	//Mask Timer 2
	(*INTMSK) |= BIT11;
}

//
// ----- intTimer2isr --------------------------------
//
cyg_uint32 intTimer2isr(cyg_vector_t vector, cyg_addrword_t data)
{
	//Tell the processor that we have received
	//the interrupt
	cyg_interrupt_acknowledge(vector);

	//
	// my code
	//
	//@ debug only move the IO
	(*PDATF) |= BIT4;
	(*PDATF) &= ~BIT4;

	//Block this interrupt from occurring until
	//the DSR completes
	cyg_interrupt_mask(vector);

	//Tell the kernel that chained interrupt processing 
	//is done and the DSR needs to be executed next
	return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}

//
// ----- intTimer2dsr --------------------------------
//
void intTimer2dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
	//signal the thread to run for further processing
	cyg_semaphore_post(&data_ready);

	//allow this interrupt to occur again
	cyg_interrupt_unmask(vector);
}

/////////////////////////////////// END ////////////////////////////////////////

/*
//
// ----- intTimer2isr --------------------------------
//
cyg_uint32 intTimer2isr(cyg_vector_t vector, cyg_addrword_t data)
{
	//Block this interrupt from occurring until
	//the DSR completes
	cyg_interrupt_mask(vector);

	//Tell the processor that we have received
	//the interrupt
	cyg_interrupt_acknowledge(vector);
	
	//
	// my code
	//
	(*PDATF) |= BIT4;
	(*PDATF) &= ~BIT4;

	//Tell the kernel that chained interrupt processing 
	//is done and the DSR needs to be executed next
	return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
*/