This is the mail archive of the mailing list for the eCos project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [ECOS] [SMP]serious bug in synchronisation primitives

A quick solution (for time being) that can take care of majority (haven't looked if it will take care of all the situations) of problem situations, would be to do CYG_KERNEL_CPU_THIS() involving array accesses in simple inline accessor functions in sched.hxx under disable---restore interrupts protection, to ensure that invoking thread does not get scheduled out in middle of it.

however it is a costly solution, considering that these inlines would be called quite often. if possible, better solutions would be preferrable.

in case we go with disable--restore model to handle the problem in global way, could it be possible to have slightly separate names macros for disabling--restoring the interrupts here?

considering the SMP HAL i have worked with so far, i would prefer using slightly tweaked versions/ asm-inlines if needed, that reduce the instructions involved in the process as compared to normal DISABLE-RESTORE, taking advantage of the fact that I need to do it for a very small section of code, for a small time and that no switching etc. will be happening during it.

if modifications were to be done in HAL, would have done by now. would avoid making modifications in non-HAL code as far as possible, to make it convenient to keep in sync with regular eCos cvs.

as one colleague mentioned, this could be possibly last stumbling block in getting a stable SMP eCos on SOC architecture we have worked upon.

comments/feedbacks awaited.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]