Re: Minor fix for CortexM vectors.S

[Nick Garnett <nickg at ecoscentric dot com>]

Chris Holgate <chris@zynaptic.com> writes:

> Hi folks,
> 
> This is a minor fix that I found while building the ROM based target for
> my STM32 board.  The hal_switch_state_vsr can generate invalid
> EXC_RETURN values in the link register for certain alignments - the fix
> is to ensure that bit 1 is always cleared.  It's also possible to
> reclaim a bit of RAM for the interrupt stack:

I'm not sure about either of these.

The stack reset is benign. However, on other targets we often assign a
few words padding at the top of the interrupt stack to allow for
errant ISRs. There's no proof that this has ever been necessary, so
it is just a safety margin. By not adjusting the stack here, we got
that buffer zone implicitly.

I'm not sure I understand the change to LR. Normally the SWI from the
reset VSR should set LR to 0xFFFFFFF1, a return to handler mode on the
main stack. The state switch VSR sets it to 0xFFFFFFFD, a return to
thread mode on the process stack. The only other valid value would be
0xFFFFFFF9, a return to thread mode on the main stack, which we never
use. None of these has bit 0x2 set, so I'm not sure what problem you
are seeing that requires this bit to be cleared. I don't see how
alignment can affect this bit, or the LR value here at all.



> 
> *** cvs-14.11.08/ecos/packages/hal/cortexm/arch/current/src/vectors.S
> 2008-11-03 14:53:51.000000000 +0000
> ---
> working-14.11.08/ecos/packages/hal/cortexm/arch/current/src/vectors.S
> 2008-11-18 11:10:31.000000000 +0000
> ***************
> *** 129,140 ****
> --- 129,142 ----
>           isb                             // Insert a barrier
>           
>           msr     psp,sp                  // Copy SP to PSP
> +         ldr     sp,=hal_startup_stack   // Reset SP to top of RAM
>   
>   #if !defined(CYGPKG_KERNEL)
>           sub     sp,#(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE/2)
>   #endif        
>           
>           orr     lr,#0xD                 // Adjust return link
> +         bic     lr,#0x2
>           bx      lr                      // Return to init code on PSP
> 
> Chris.
> 

-- 
Nick Garnett                                      eCos Kernel Architect
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