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Re: Synth NAND Flash
- From: Simon Kallweit <simon dot kallweit at intefo dot ch>
- To: "ecos-devel at ecos dot sourceware dot org" <ecos-devel at ecos dot sourceware dot org>
- Cc: Rutger Hofman <rutger at cs dot vu dot nl>
- Date: Tue, 12 May 2009 10:36:34 +0200
- Subject: Re: Synth NAND Flash
- References: <4A0855FB.firstname.lastname@example.org>
Simon Kallweit wrote:
Now for the actual design of the synth driver. I think the best way
would be to implement a NAND simulator based on the ONFI specification.
Something similar has been done for the MTD framework, but I guess other
than for inspiration we're not allowed to use that code. So basically we
would simulate the interface to the chip. I guess we don't have to
simulate the signal lines. We just need some mechanism for chipselect
and reset I guess. The interface will more be along the lines of writing
commands, addresses, reading back etc. This means that the simulator
will be implemented as a state machine. There is even one described in
the ONFI specification for reference.
Well after some more thought it's probably a better idea to keep the
interface to the NAND chip simulator very close to the hardware. That
means, a function for setting signal lines (CE, CLE, ALE, WP) as well as
two functions for read and write access.
I don't intend to support multiple LUNs for the moment, just to keep it
I have already done the interface to the NAND chip simulator. This seems
to work fine. I'll keep you updated.