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Re: Re: NAND technical review


Rutger Hofman wrote:

<snip>
- R's model shares the command sequence logic amongst all chips,
differentiating only between small- and large-page devices. (I do not
know
whether this is correct for all current chips, though going forwards
seems
less likely to be an issue as fully-ONFI-compliant chips become the
norm.)
Hmm. Nevertheless, this is a concern for me with R's. I'm concerned it
may be too prescriptive to be robustly future-proof.

Well, there is no way I can see into the future, but I definitely think that the wire command model for NAND chips is going to stay -- it is in ONFI, after all. Besides, all except the 1 or 2 most pioneering museum NAND chips use it too. There are chips that use a different interface, like SSD or MMC or OneNand, but then these chips come with on-chip bad block management, wear leveling of some kind, and are completely different in the way they must be handled. I'd say E's and R's implementations are concerned only with 'raw' NAND chips.

Correct, only for raw NAND chips to be soldered on a board. The others have an embedded controller and are already packaged.
One could say that makes it a more realistic emulation. But yes I can
see disadvantages with a somewhat rigid world view. Thinking out loud, I
wonder if Rutger's layer could work with something like Samsung OneNAND.

See my comment above. The datasheet on e.g. KFM{2,4}G16Q2A says: "MuxOneNAND™‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface."

Indeed, a oneNAND is to be threated as a NOR flash, like a pseudoSRAM is a DRAM with SRAM interface.
And SSD has a hard disk drive interface, just like MMC and SD card; they mostly have a FAT file system on them but also UFS ...


Kind regards,
Jürgen


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