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Re: Cortex-M3 HAL interrupt-priority code bug
- From: Nick Garnett <nickg at ecoscentric dot com>
- To: Nagaraj K <nagaraj dot kmurthy at gmail dot com>
- Cc: ecos-devel at ecos dot sourceware dot org
- Date: 25 Nov 2010 11:19:03 +0000
- Subject: Re: Cortex-M3 HAL interrupt-priority code bug
- References: <AANLkTikH4CxinV6F9SNPC1Btr1byV_HuJaOSQMAz1bAX@mail.gmail.com>
Nagaraj K <nagaraj.kmurthy@gmail.com> writes:
> I see that this function wrongly implements the priority level in
> Cortex-M3 processor. According to the Cortex-M3 data sheet, we need to
> write the priority level to the top N bits of the register where N is
> the number of priority level bits implemented in this particular
> version of the cortex variant.
The intention in the design of the hardware is that software can use a
256 level prioirity scheme on all implementations. By defining the
actual priority in terms of the top N bits of the registers, the
hardware essentially groups the 256 virtual priorities into a set of
real priorities by ignoring the less significant bits.
eCos simply follows the lead given by the hardware and implements 256
priorities. It is a good scheme and allows us to write code that will
work in all implementations.
--
Nick Garnett eCos Kernel Architect
eCosCentric Limited http://www.eCosCentric.com The eCos experts
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