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Nested interrupts on ARM


I found a bug with our product which boils down to a high priority interrupt not being called fast enough sometimes because we are in a different ISR (lower priority). We have CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING on, but looking through the code this does very little on ARM chips (just sets the min stack size).

Looking at packages/hal/arm/arch/current/src/vectors.S it looks like the framework for nested interrupts is in place, but during an interrupt the IRQ bit in the CPSR register is never cleared. I wrote the following patch, which enables IRQs runs the ISR and disables IRQs again. This works, and I can now see nested interrupts working, however I'm now seeing it take 30us to get into my high priority ISR when I'm already in an ISR, rather than the 7us when I'm not already in an ISR.

So my questions:
1) Does my patch make sense?
2) Any idea why this wasn't already in place? It seems like something so simple must have been left out for a reason. 3) Any idea on the 30us to get into my ISR? This may be the first ISR disabling IRQs for a bit, I need to look more into this area.

Thanks,
Andrew Parlane
Carallon Ltd.


--- a/packages/hal/arm/arch/current/src/vectors.S
+++ b/packages/hal/arm/arch/current/src/vectors.S
@@ -914,7 +914,14 @@ IRQ:
 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS
         b       spurious_IRQ

-10:     ldr     r1,.hal_interrupt_data
+10:
+        // re-enable IRQs so we can have nested interrutps
+        ARM_MODE(r1,10)
+        mrs     r1,cpsr
+        bic     r1,r1,#CPSR_IRQ_DISABLE
+        msr     cpsr, r1
+
+        ldr     r1,.hal_interrupt_data
         ldr     r1,[r1,v1,lsl #2]       // handler data
         ldr     r2,.hal_interrupt_handlers
         ldr     v3,[r2,v1,lsl #2]       // handler (indexed by vector #)
@@ -926,6 +933,11 @@ IRQ:
         mov     lr,pc                   // invoke handler (call indirect
         bx      v3                      // thru v3)

+        // disable IRQs
+        mrs     r1,cpsr
+        orr     r1,r1,#CPSR_IRQ_DISABLE
+        msr     cpsr, r1
+
 spurious_IRQ:


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