Re: [ECOS] ppc603e cache sync

[Jesper Skov <jskov@cygnus.co.uk>]

daniel> Maybe this isn't the right forum for this but:

daniel> I need to flush the cache on an MPC8240, which is basicly a
daniel> ppc603e.  One way of doing this is to zero the cache with a
daniel> dummy area, this area need not be specially aligned, and could
daniel> be put into the .bss section.
 
daniel> - - In which source file would it be logical to place it?

daniel> - - and what should that area be named?

The few other CPUs that have to do this use either a dedicated chunk
of the address space or read from the ROM. See the TX39 var_cache.h
file.

The only other place were we do this by steam is in the kcache
tests. There the array is called 'dca' - data cache array or some
such. Not something that has been blessed with official policy (yet).

daniel> Maybe someone could suggest a neater solution?

Doesn't it have the implementation specific flush-all command as the
603? I don't have my manuals close by, unfortunately, but the 603
definitely has a one-shot operation for flushing (or is it clearing?)
the cache.

If not, maybe something like the below would be better (from my
Linux/APUS sources):

#define L1_CACHE_BYTES 32
#define MAX_CACHE_SIZE 8192
__apus
void cache_push(__u32 addr, int length)
{
        addr = mm_ptov(addr);

        if (MAX_CACHE_SIZE < length)
                length = MAX_CACHE_SIZE;

        while(length > 0){
                __asm ("dcbf 0,%0\n\t"
                       : : "r" (addr));
                addr += L1_CACHE_BYTES;
                length -= L1_CACHE_BYTES;
        }
        /* Also flush trailing block */
        __asm ("dcbf 0,%0\n\t"
               "sync \n\t"
               : : "r" (addr));
}

Jesper