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RE: cyg_drv_interrupt_create ()


Ok, thanks.  I'll look into the eCos hal, and see what I can do.

> -----Original Message-----
> From: Lewin A.R.W. Edwards [mailto:larwe@larwe.com] 
> Sent: Friday, June 22, 2001 9:06 AM
> To: Trenton D. Adams
> Cc: ecos-discuss@sources.redhat.com
> Subject: RE: [ECOS] cyg_drv_interrupt_create ()
> 
> 
> 
> > > the remainder are routed to IRQ (CODEC, the three EINT pins, TC1 
> > > underflow,
> >
> >So you're saying that there are acutally only one IRQ, and 
> one FIQ, but 
> >there are three EINT pins?
> 
> Correct. The interrupt controller is conceptually a 
> multi-input OR gate and 
> a latch. When the CPU receives an interrupt from whatever source, the 
> appropriate bit in the latch is set. The outputs of the latch 
> are ORed 
> together (all the FIQs are ORed to a single FIQ request line on the 
> processor core, and all the IRQs are ORed to a single IRQ 
> request line on 
> the processor core). There is no vectoring performed by the 
> processor. If 
> you cause an nEINT3, all the CPU knows is that it got an IRQ. It's 
> software's responsibility, in the IRQ ISR, to read the state 
> of the latches 
> (INTSR1/2/3) and determine who caused the interrupt.
> 
> (The hardware implementation is more complicated than that, 
> of course, but 
> conceptually it works as above).
> 
> 
> -- Lewin A.R.W. Edwards
> Embedded Engineer, Digi-Frame Inc.
> Work: http://www.digi-frame.com/
> Tel (914) 937-4090 9am-6:30pm M-F ET
> Personal: http://www.larwe.com/ http://www.zws.com/
> 
> "Far better it is to dare mighty things, to win glorious 
> triumphs, even 
> though checkered by failure, than to rank with those poor spirits who 
> neither enjoy much nor suffer much, because they live in the 
> gray twilight 
> that knows not victory nor defeat."
> (Theodore Roosevelt)
> 
> 


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