This is the mail archive of the ecos-discuss@sources.redhat.com mailing list for the eCos project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

Re: RM7000 interrupt handling



Chris Morrow <cmorrow@YottaYotta.com> writes:
> For the mips architecture HAL_INTERRUPT_MASK is defined as
> follows;
> 
> #define HAL_INTERRUPT_MASK( _vector_ )          \
> CYG_MACRO_START                                 \
>     asm volatile (                              \
>         "mfc0   $3,$12\n"                       \
>         "la     $2,0x00000400\n"                \
>         "sllv   $2,$2,%0\n"                     \
>         "nor    $2,$2,$0\n"                     \
>         "and    $3,$3,$2\n"                     \
>         "mtc0   $3,$12\n"                       \
>         "nop; nop; nop\n"                       \
>         :                                       \
>         : "r"(_vector_)                         \
>         : "$2", "$3"                            \
>         );                                      \
> CYG_MACRO_END
> 
> It is possible to get an interrupt between the mfco and mtco.
> As long as the status register is not modified as part of
> interrupt processing this is not a problem.

Right.  But that can happen, and I agree that you have found a bug.

But for many [all?] platforms those macros in the arch HAL are not used;
the variant or platform HAL supplies them, because the platform has an
external PIC or some other mask register for additional interrupt sources.

Looks like some MIPS platforms, but not all, have a similar bug. ;-(

	- Huge


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]