Re: [ECOS] RM7000 interrupt handling

[Robin Farine <acnrf at dial dot eunet dot ch>]

Mark Salter <msalter@redhat.com> writes:

[...]

> I think the bug would be an ISR that changes the status register.
> 
> There is no atomic way of disabling interrupts on the MIPS architecture.
> You have to read the status register, modify it, then write it back.

If I remember well, the restrictions below avoid such problems:

1. the startup code presets the per-source interrupt bits and they never change
   after that; code should use the devices internal interrupt controllers to
   enable/disable interrupt sources.

2. the interrupt VSR and ISRs use the master interrupt bit only => no nested
   interrupts

3. the rest of the code can safely disable and restore interrupts using the
   master interrupt bit only;

What do you think, too much restrictive for eCos?

Robin