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powerpc serial driver


hi

i am writing on a SCC UART driver for eCos, and
derived it from the existing SMC driver. 

i made some changes to get it working. here
are the changes for the SMC driver.

i could not test it, not even compile it.
( i do not have a SMC serial port).

It concerns flushing the cache before 
flushing the device.

best regards, christoph

-- 
--- quicc_smc_serial.c	Fri Nov  9 10:34:03 2001
+++ quicc_smc_serial.c.new	Fri Nov  9 10:18:49 2001
@@ -54,6 +54,9 @@
 
 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
 
+// macro for aligning buffers to cache lines
+#define ALIGN_TO_CACHELINES(b,s) (((unsigned long)(b) + (s-1)) & ~(s-1))
+
 // Buffer descriptor control bits
 #define QUICC_BD_CTL_Ready 0x8000  // Buffer contains data (tx) or is empty (rx)
 #define QUICC_BD_CTL_Wrap  0x2000  // Last buffer in list
@@ -398,11 +401,11 @@
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE,
-                                   &quicc_smc1_txbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0][0], 32),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
-                                   &quicc_smc1_rxbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0][0], 32),
                                    0xC0, // PortB mask
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
                                    12  // SI mask position
@@ -430,11 +433,11 @@
                                    TxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE,
-                                   &quicc_smc2_txbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0][0], 32),
                                    RxBD, 
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
-                                   &quicc_smc2_rxbuf[0][0],
+                                   (cyg_uint8 *)ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0][0], 32),
                                    0xC00, // PortB mask
                                    CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG,
                                    28  // SI mask position
@@ -475,6 +478,13 @@
 quicc_smc_serial_flush(quicc_smc_serial_info *smc_chan)
 {
     volatile struct cp_bufdesc *txbd = smc_chan->txbd;
+    int cache_state;
+                                       
+    HAL_DCACHE_IS_ENABLED(cache_state);
+    if (cache_state) {
+      HAL_DCACHE_FLUSH(txbd->buffer, scc_chan->txsize);
+    }
+
     if ((txbd->length > 0) && 
         ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0)) {
         txbd->ctrl |= QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int;  // Signal buffer ready

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