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Re: hal_sh_sh750_cq7750.cdl
- From: Jesper Skov <jskov at redhat dot com>
- To: Koichi Nagashima <knaga at r-lab dot co dot jp>
- Cc: ecos-discuss at sources dot redhat dot com
- Date: Mon, 19 Nov 2001 12:49:59 +0100
- Subject: [ECOS] Re: hal_sh_sh750_cq7750.cdl
- References: <20011119.153915.41630943.knaga@r-lab.co.jp>
In the future, please post your comments directly to the
list. Thanks.
>>>>> "Koichi" == Koichi Nagashima <knaga@r-lab.co.jp> writes:
Koichi> I has built eCos/RedBoot from anon'-CVS source tree, but the
Koichi> built image can't communicate with my host via serial port.
Koichi> I looked at the sources and disassembled codes, then I found a
Koichi> miss-configuration in hal_sh_sh750_cq7750.cdl.
Koichi> The option of CYGHWR_HAL_SH_OOC_DIVIDER_1 seems to be
Koichi> required, but there is no definition in
Koichi> hal_sh_sh750_cq7750.cdl.
True. It's an oversight. Results in bad clocks, apparently. I've
committed the below patch (different from yours).
Thanks,
Jesper
Index: ChangeLog
===================================================================
RCS file: /local/cvsfiles/ecc/ecc/hal/sh/cq7750/current/ChangeLog,v
retrieving revision 1.14
diff -u -u -5 -r1.14 ChangeLog
--- ChangeLog 11 Sep 2001 17:41:37 -0000 1.14
+++ ChangeLog 19 Nov 2001 11:48:16 -0000
@@ -1,5 +1,10 @@
+2001-11-19 Jesper Skov <jskov@redhat.com>
+
+ * cdl/hal_sh_sh7750_cq7750.cdl: Added CYGHWR_HAL_SH_OOC_DIVIDER_1
+ (found by Koichi Nagashima)
+
2001-09-11 Jonathan Larmour <jlarmour@redhat.com>
* cdl/hal_sh_sh7750_cq7750.cdl: Default to big endian.
2001-08-08 Jesper Skov <jskov@redhat.com>
Index: cdl/hal_sh_sh7750_cq7750.cdl
===================================================================
RCS file: /local/cvsfiles/ecc/ecc/hal/sh/cq7750/current/cdl/hal_sh_sh7750_cq7750.cdl,v
retrieving revision 1.7
diff -u -u -5 -r1.7 hal_sh_sh7750_cq7750.cdl
--- cdl/hal_sh_sh7750_cq7750.cdl 11 Sep 2001 17:41:37 -0000 1.7
+++ cdl/hal_sh_sh7750_cq7750.cdl 19 Nov 2001 11:47:50 -0000
@@ -150,10 +150,21 @@
This selects the multiplication factor provided by
PLL2. If PLL2 is disabled this option should
be set to zero."
}
+ cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
+ display "SH clock first clock divider"
+ flavor data
+ legal_values { 1 2 }
+ default_value 1
+ no_define
+ description "
+ First stage clock divider according to the mode (MD0..2).
+ Set 2 for mode 2 and 4, otherwise set 1."
+ }
+
cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
display "SH CPU clock divider"
flavor data
default_value 1
legal_values { 1 2 3 4 6 8 }