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Re: interrupt_end


On Fri, Feb 15, 2002 at 10:54:04AM +0900, Motoya Kurotsu wrote:

> hal_cpu_except_enable

So I think that the hal_cpu_except_enable is not correct. 
I see the current one such like the following in arch.inc.

        .macro hal_cpu_except_enable
        mfc0    v0,status
        la      v1,0xFFFFFFF0
        and     v0,v0,v1                # clear EXL, ERL and IE bits
        mtc0    v0,status
        nop
        nop
        nop
        .endm

I think that it should be the following:

        .macro hal_cpu_except_enable
        mfc0    v0,status
        la      v1,0xFFFFFFF9
        and     v0,v0,v1                # clear EXL and ERL bits
        ori     v0,v0,0x0001            # set IE bit
        mtc0    v0,status
        nop
        nop
        nop
        .endm

As you see, the original one clears a part of KSU bit. It also needs 
to be fixed, doesn't it?

Thanks,
Motoya Kurotsu
Allied Telesis K.K.



On Thu, Feb 14, 2002 at 07:38:10PM +0000, Jonathan Larmour wrote:
> Motoya Kurotsu wrote:
> > 
> > Hi all,
> > 
> > Is my understanding correct that the interrupt_end which is defined
> > in hal/common must be called with interrupts enabled?
> > I am seeing mips/arch/currect/src/vector.S, but I can't specify
> > where interrupt is reenabled before the interrupt_end is called
> > in default interrupt VSR.
> 
> hal_cpu_except_enable
> 
> Jifl
> -- 
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