[ECOS] On ecos interrupt process

[=?gb2312?B?1cUgwcE=?= <johnsonest at hotmail dot com>]

Hi ,all.
  how on earth a interrupt was processed?
  here is a procedure:

  a thread is running when  corresponding bit of interrupt pending 
rigister was set.in succession, how cpu to do? "pc" changes to vsr entry 
automatically and some core  rigisters was saved automatically ?
  i issue this question because i find following code in  default 
exception
vsr():
    cyg_hal_default_exception_vsr:
       
       # We come here with all register containing their
       # pre-exception values except:!!!!!!i want know  how R3,R4,R5 be 
filled with vector,CR,LR before coming here!
       # R3    = ls 16 bits of vector address
       # R4    = saved CR
       # R5    = saved LR
       # LR    = VSR address
       # SPRG1 = old R3
       # SPRG2 = old R4
       # SPRG3 = old R5
       # SRR0  = old PC
       # SRR1  = old MSR and the exception cause (the POW state is lost!)

       subi    sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT
                                       # leave space for registers and
                                       # a safety margin

       # First, save away some registers
       stw     r3,CYGARC_PPCREG_VECTOR(sp)    # stash vector
       stw     r4,CYGARC_PPCREG_CR(sp)        # stash CR
       stw     r5,CYGARC_PPCREG_LR(sp)

and  another question:
   till here, all code should be executed on current thread stack,right?

tks&regards
                                                            zhlg     
  

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