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Re: Big endian ARM HAL_WRITE_UINT8 problem (ecos 1.3.1)


> You are using register definitions that are munged for big-endian
> hardware and clearly expected to be used by non-portable (big/little
> endian) software.

> If you want to use them with eCos macros, it will clearly fail since the
> eCos macros are endian safe.

> How's that? Well, the device you are writing to is activated (chip
> select) by matching of address lines A31-A2. I.e. addresses 0x71c,
> 0x71d, 0x71e and 0x71f all match and enable your device for access. It
> doesn't care about anything else.

> So when the chip select is right, you need to get the data bits right.
> Depending on the endianess of the CPU, you need to put the data in
> either D0-7 or D24-D31 for 8bit access. You do that by changing A1-A0.

> So A1-A0 should be depending on the CPU endian mode, and *nothing else*.

> If you don't care about portability, and want to use definitions that
> are not suitable for porting, by all means don't use the eCos macros.

> But don't blame the macros for bothing it when fed bad definitions. The
> macros do exactly what they were designed to; making the software
> portable. Changing one endian definition flag is easier than changing
> umpteen register definitions.

Maybe its me, but it seems you are describing broken hardware. The
bus subsystem (external to the CPU) should be responsible for 
handling the byte lanes correctly. On bi-endian boards, this usually
means adding a jumper/switch so that the bus controller knows what
endianness to use. If a bi-endian board requires different addresses
for byte registers depending on endianess, then it is broken IMO. Some
XScale boards that I am familiar with do not require address gymnastics
based on endianess. A byte address is the same with both endianesses.

--Mark

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