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Re: GDB support in ARM thumb mode
- From: Mark Salter <msalter at redhat dot com>
- To: richintervideo at yahoo dot com
- Cc: ecos-discuss at sources dot redhat dot com
- Date: Tue, 27 Aug 2002 08:51:19 -0400
- Subject: Re: [ECOS] GDB support in ARM thumb mode
- References: <20020827060226.23142.qmail@web14909.mail.yahoo.com>
>>>>> Rich LeGrand writes:
> Hi all,
> I noticed something in vectors.S (for ARM) that has been causing us some
> problems. Around line 584:
> // switch to pre-exception mode to get banked regs
> mov r0,sp // r0 survives mode switch
> mrs r2,cpsr // Save current psr for return
> orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
> msr cpsr,r1
> Here, r1 contains the SPSR. If we set a debugging breakpoint in thumb code and
> enter the above code through the illegal instruction exception, the msr
> instruction above will necessarily set the T bit, which is bad. Masking the
> mode bits such as:
> // switch to pre-exception mode to get banked regs
> mov r0,sp // r0 survives mode switch
> mrs r2,cpsr // Save current psr for return
> bic r4,r2,#CPSR_MODE_BITS // clear mode bits
> and r1,r1,#CPSR_MODE_BITS // isolate mode bits
> orr r1,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
> msr cpsr,r1
> seems to fix this issue. That is, when attaching GDB to Redboot (running in
> thumb) before the change, GDB would hang. After the change, we can attach GDB
> and load the program, but we notice problems later when we encounter
> breakpoints that we set.
> Has there been much testing with debugging ARM thumb code lately? (since
> vectors.s was changed significantly 3 months ago.)
Very interesting.
Yes, we tested debugging by running the GDB testsuites using normal mode, thumb mode,
and thumb-interwork. There we no regressions. But I think most (if not all) testing
was on XScale cores which are V5TE. I think that different pipelines are the reason
it works on one, but not the other. The code does this:
msr cpsr,r1 // switch to pre-exception mode
stmfd r0!,{r8-r12,sp,lr} // load regs
msr cpsr,r2 // back to svc mode
The proper way to switch in and out of thumb mode is with an insn that changes the
PC (such as 'bx') because that causes a pipeline flush. If you don't have a pipeline
flush, there is ambiguity about when the mode change actually takes place. In the
bit of code above, the stmfd is already in the pipeline as a normal mode insn. The
same *should* be true of the following msr. That must be the case for v5t or the
code would fail. I would expect the same to be true for arm7, but *shrug*.
Anyway, you are correct that the code should clear the T bit so that ambiguity is
removed. This patch should fix the three places where this comes up. Give it a
try and let us know if it fixes your problem.
--Mark
*** vectors.S.~1.46.~ Thu May 23 19:01:42 2002
--- vectors.S Tue Aug 27 08:49:30 2002
***************
*** 585,590 ****
--- 585,591 ----
mov r0,sp // r0 survives mode switch
mrs r2,cpsr // Save current psr for return
orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r1,r1,#CPSR_THUMB_ENABLE
msr cpsr,r1
stmfd r0!,{r8-r12,sp,lr}
msr cpsr,r2 // back to svc mode
***************
*** 644,649 ****
--- 645,651 ----
add r2,sp,#armreg_r8
mrs r1,cpsr
orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r0,r0,#CPSR_THUMB_ENABLE
msr cpsr,r0
ldmfd r2,{r8-r14}
msr cpsr, r1 // back to svc mode
***************
*** 724,729 ****
--- 726,732 ----
mov r0,sp // r0 survives mode switch
mrs r2,cpsr // Save current psr for return
orr r1,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
+ bic r1,r1,#CPSR_THUMB_ENABLE
msr cpsr,r1
stmfd r0!,{r8-r12,sp,lr}
msr cpsr,r2 // back to svc mode
--
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