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AEB rev C cache fixed?
- From: Guillermo Rodriguez Garcia <guille at iies dot es>
- To: ecos-discuss at sources dot redhat dot com
- Date: Thu, 21 Nov 2002 23:45:46 +0100
- Subject: [ECOS] AEB rev C cache fixed?
Hello all,
Some time ago I was having trouble with the cache on the AEB board and
I saw this on hal/arm/aeb/current/include/hal_platform_setup.h (this was
revision 1.5 from CVS)
// AEB rev C has 256kB of memory. Cache is working (set cachable)
#if 0
#define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04
#define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
#else
// FIXME: There is a cache problem of some sort. Either eCos or the
// chip. Leave cache disabled till I find the time to fix it. Jesper
#define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007804
#define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
#endif
Back then I asked on the list but nobody knew how to fix the problem.
Now I see that on the transition from revision 1.5 to 1.6, this has
been changed to the following:
// AEB rev C has 256kB of memory. Cache is working (set cachable)
#define AEB_SRAM .long 0xFFFFA008,0x00008000,0x00048000,0x00007c04
#define AEB_BAD .long 0xFFFFA00C,0x00048000,0x01000000,0x00000000
#define AEB_CACHE .long 0xFFFFA010,0x60000000,0x61000000,0x00007801
Does this mean that the cache is now working on AEB revision C? If so,
can someone explain what was exactly the problem? Why is this AEB_CACHE
segment needed? (from my understanding of the lh77790 documentation,
this should only be necessary when using the cache in SRAM mode, which
doesn't seem to be the case here)
Many thanks in advance,
G.
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