This is the mail archive of the
ecos-discuss@sources.redhat.com
mailing list for the eCos project.
Re: Question about the ARM vector.S?
- From: Andrew Lunn <andrew dot lunn at ascom dot ch>
- To: Qiang Huang <jameshq at liverpool dot ac dot uk>
- Cc: Ecos-Discuss <ecos-discuss at sources dot redhat dot com>
- Date: Thu, 23 Jan 2003 12:10:29 +0100
- Subject: Re: [ECOS] Question about the ARM vector.S?
- References: <BDEPKKELILOKGOAOMONOMEBNCBAA.jameshq@liv.ac.uk>
On Thu, Jan 23, 2003 at 11:06:31AM -0000, Qiang Huang wrote:
> Hi all:
> while installing the vector table use the table to store the VSR address
> as:
>
> ldr pc,.reset_vector // 0x00
> ldr pc,.undefined_instruction // 0x04
> ldr pc,.software_interrupt // 0x08 start && software
> int
> ldr pc,.abort_prefetch // 0x0C
> ldr pc,.abort_data // 0x10
> .word 0 // unused
> ldr pc,.IRQ // 0x18
> ldr pc,.FIQ // 0x1C
> vectors:
> UNMAPPED_PTR(reset_vector) // 0x20
> PTR(undefined_instruction) // 0x24
> PTR(software_interrupt) // 0x28
> PTR(abort_prefetch) // 0x2C
> PTR(abort_data) // 0x30
> .word 0 // 0x34
> PTR(IRQ) // 0x38
> PTR(FIQ) // 0x3c
>
> Can I use the "LDR pc,=reset_vector" ... etc. ARM pseudo-instruction to
> replace the "ldr pc,.reset_vector" and eliminate the table for storing the
> VSR address? Thanks a lot.
The resulting code has to be 1 instruction. The hardware dictates that
word 0 is the reset vector, word 1 is the undefined_instruction vector
etc. If the pseudo-instructions is two real instructions, the
undefined_instruction vector is actually going to contain part of the
reset vector instruction....
Andrew
--
Before posting, please read the FAQ: http://sources.redhat.com/fom/ecos
and search the list archive: http://sources.redhat.com/ml/ecos-discuss