Re: [ECOS] SH3 77x9SE01 bug

[Jonathan Larmour <jifl at eCosCentric dot com>]

Rod Campbell wrote:
> While attempting to build support for the 7729R, I found what I think is
> a bug in the existing 77x9SE01 platform.  I am using eCos V 2.0b1
>
> The setting for the oscillator control Divider2 divide-by-6 is
> incorrect.  This causes an illegal FRQCR value to be built and you won't
> get a reliable boot up from reset (I could get the system to boot about
> 1 out of 25 times).

I believe you that this causes problems in your case, but if so, I would 
be surprised this wasn't noticed when it was originally developed. I'm 
pretty sure the ports we were using were very reliable. Is the setting 
board specific and it was a slightly different board variant maybe? After 
all the se77x9 platform HAL is meant to support the 7709RP01, 7709SE01 and 
7729SE01 boards. Unfortunately I can't remember which (one, two or all) of 
these the port was originally written for.

If you can persuade me your change is legitimate I'll make it :). 
Unfortunately I don't have any hardware myself to corroborate, sorry. But 
if you can check in the ref manuals for these boards to check that this 
value is correct for all the boards then fair enough. If it's only correct 
for some of the boards then we can look at making it configurable 
depending on the board.

>  Also, the SCIF2 serial port won't work (bad baud
> rate generation because of incorrect peripheral clock value).  
> In /packages/hal/sh/sh3/v2_0b1/include/mod_regs_cpg.h
> For the V3 (last) group of conditional compilation statements,
> following the statement #elif (CYGHWR_HAL_SH_00C_DIVIDER_2 == 6)
> change from: # define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2002
>        to:   # define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2001

I'm slightly more inclined to believe you here because it's possible SCIF2 
wasn't tested. But again, given what you wrote above, I think we should 
check this applies to all the board variants first.

Jifl
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