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bug in mips arch code ????
- From: "HG" <henri at broadbandnetdevices dot com>
- To: <ecos-discuss at sources dot redhat dot com>
- Date: Fri, 2 May 2003 09:05:51 -0400
- Subject: [ECOS] bug in mips arch code ????
- Organization: BND
- Reply-to: "HG" <henri at broadbandnetdevices dot com>
Hi All
1- interrupt acknowledge
the macro HAL_INTERRUPT_ACKNOWLEDGE found in /mips/arch/hal_intr.h tries to
write in a region of the cause register ($13) that is read only ( the ip
bits 10 to 15) . As per the Sweetman book and the idt mips ref manual ,
these bits show the interrupts that want to happen. To acknowledge those
hardware interrupt(s) , the condition is cleared by correcting the
condition causing the interrupt pin to be asserted.
example : the vector 1 causes an attempted write to bit 11 of the cause cp0
register
while this does not break anything , what is broken is that the routines
think they are acknowledging the interrupt but they are not.
in the case of the timer interrupt , the isr in clock.cxx calls the
HAL_CLOCK_RESET macro that does a write to the compare register ($11) . As
per the mips documentation this is what is required to acknowledge the
interrupt and deassert the interrupt request. All is well.
in the case of the 82559 interrupt , the datasheet indicates that a write to
some bits of the SCB command word is required.
"SCB Command Word: The CPU places commands for the Command and Receive units
in
this register. Interrupts are also acknowledged in this register. "
When no macro to write to these bits is written , the driver defaults (after
many defines ) to the above HAL_INTERRUPT_ACKNOWLEDGE .
the comments related to the chip being "wedged" may be related to this
condition.
a clean way to fix this is to define the macros found in the comments
section of the 82559 driver :
// Platform code can also define these three:
// CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old)
//
CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old)
// CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559)
some of the platforms appear to define this, none of the mips boards do
however. The platforms that do dont appear to follow the datasheets
recommendation???? . I will write and test those macros for my platform and
contribute them to the patch list in the form of source code that the
maintainers of the specific boards can use to generate patches for the
specifics of their board.
2- Interrupt state control
the documentation found in the reference manual appears to contradict some
of the macros in mips/arch/include/hal_intr.h :
from the documentation
HAL_DISABLE_INTERRUPTS(old) disables the delivery of interrupts and stores
the original state of the interrupt mask
in the variable passed in the old argument.
from the code :
the macro saves only the ie bit (global interrupt enable) but does not save
the im field (interrupt mask)
any help in this matter is appreciated
thanks
Henri
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