[ECOS] please help on memory layout and other questions.

["Ka Chun, Cheng" <kccheng at biblecrawler dot com>]

ok my serial port and debug LED(direct GPIO output) are working but I'm
still confused by the memory layout.
flash physical: 0x00000000, 32M byte
ram physical : 0xA0000000, 64M byte

to my understanding.....
all the address in source, ldi and mlt files are talking about virtual
address, except places stated clearly.
so the code is compiled and linked with virtual address. the system init
code should be simple enough, able to run in physical address during first
boot from flash.

when the system boot for the first time from flash, the cpu is running with
mmu off, flash at 0x00000000 and ram at 0xA0000000. that is PLATFORM_SETUP
macro. the macro call hal_mmu_init(), the MMU is setup there. after the
macro control go back to redboot package. the program is copied to RAM
somehow, and system is soft reset so that the program restart with mmu on.
ram is now mapped at 0x00000000 and rom at 0x50000000. platform_setup is run
again, with mmu on. finally control go back to redboot, and it will call the
other device init code.


am I right about it? please correct me or give me some pointer to the
correct system init progress.

the most confusing to me is, in mlt_arm_xscale_uE250_rom.mlt, all the rom
location say F0000000, why???
to my understanding flash physical is 0, virtual is 50000000, why F?? am I
missing something?

If I state virtual address in mlt and ldi files, my redboot do nothing. if I
state physical address in mlt and ldi files, the program run and I see my
debug message from platformsetup macro. and then it crash somewhere out of
my scope... :(

please help... thanks in advance.

void
hal_mmu_init(void)
{
    // Set up the translation tables at offset 0x4000
    unsigned long ttb_base = PXA2X0_RAM_BANK0_BASE + 0x4000;
    unsigned long i;

    rvputstr("\r\nhal_mmu_init\r\n");
    /*
     * Set the TTB register
     */
    rvputchar('1');
    asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
    rvputchar('2');
    /*
     * Set the Domain Access Control Register
     */
    i = ARM_ACCESS_DACR_DEFAULT;
    asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
    rvputchar('3');
    /*
     * First clear all TT entries - ie Set them to Faulting
     */
    memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
    rvputchar('4');
    /*               Actual  Virtual  Size   Attributes
Function  */
    /*       Base     Base     MB      cached?           buffered?
access permissions                 */
    /*             xxx00000  xxx00000
*/
#define _CACHED   ARM_CACHEABLE
#define _UNCACHED ARM_UNCACHEABLE
#define _BUF      ARM_BUFFERABLE
#define _NOBUF    ARM_UNBUFFERABLE
#define _RWRW     ARM_ACCESS_PERM_RW_RW
    X_ARM_MMU_SECTION(0x000,  0x500,    32,  _CACHED,     _BUF, _RWRW); /*
Boot flash ROMspace */
    X_ARM_MMU_SECTION(0xA00,  0x000,    64,  _CACHED,     _BUF, _RWRW); /*
DRAM Bank 0 */
    X_ARM_MMU_SECTION(0xA00,  0xC00,    64,  _UNCACHED,   _BUF, _RWRW); /*
DRAM Bank 0 */
    X_ARM_MMU_SECTION(0xE00,  0xE00,   128,  _CACHED,     _BUF, _RWRW); /*
Zeros (Cache Clean) Bank */
    X_ARM_MMU_SECTION(0x400,  0x400,    64,  _UNCACHED, _NOBUF, _RWRW); /*
Peripheral Registers */
    X_ARM_MMU_SECTION(0x440,  0x440,    64,  _UNCACHED, _NOBUF, _RWRW); /*
LCD Registers */
    X_ARM_MMU_SECTION(0x480,  0x480,    64,  _UNCACHED, _NOBUF, _RWRW); /*
Memory Ctl Registers */

    rvputchar('5');
    rvputstr("\r\n");
    }

----------------------------------------------------------------------------
--------

mlt_arm_xscale_sp263_rom.mlt, I changed all F0000000 to 50000000

version 0
region ram 0 2000000 0 !
region rom 50000000 40000 1 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section data 0 1 1 1 1 1 0 0 8000 bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 mmu_tables mmu_tables !
section mmu_tables 0 4000 0 1 0 0 0 1 data !

----------------------------------------------------------------------------
--------

in mlt_arm_xscale_uE250_rom.ldi, I changed the rom size only
// eCos memory layout - Tue Jul 02 10:03:04 2002

// This is a generated file - do not edit

#include <cyg/infra/cyg_type.inc>

MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 0x04000000
    rom : ORIGIN = 0x50000000, LENGTH = 0x02000000
}

SECTIONS
{
    SECTIONS_BEGIN
    SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA)
    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_mmu_tables (rom, ALIGN (0x4000), LMA_EQ_VMA)
    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
    SECTION_data (ram, 0x8000, FOLLOWING (.mmu_tables))
    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    SECTIONS_END
}


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