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Re: Anyone run on Intel Xeon processor?

<> writes:

> Nick,
> I have made more progress on this... I found your debug code and
> have been turning things on and adding more as needed.
> It is stalling in the code that starts the other processors. What I
> really wanted fixed is the interrupt processing for Xeons, which
> appeared to be coded if the SMP support was added.
> There is a master enable/disable bit for the APIC. The documentation
> says that it will run like a pentium 4 if this bit is set to zero. I
> am going to try that for now. I may submit it back to the group if
> it works. I am not ready to redo all of the SMP support, I really
> don't need it anyway.

Shouldn't the interrupt controller default to the standard PIC
interface? This is normally used for single processors. What are you
doing that needs the APIC?

If you really need the APIC, the best approach would be to try and
make the APIC support an independent config option from the SMP
stuff. SMP will still enable it, but it should also be settable

The only real problem with that is that the locations of the APICs and
IOAPIC is read from the MP structure. So you may have to fake that.

Nick Garnett                    eCos Kernel Architect      The eCos and RedBoot experts

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