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PCI spec Trhfa parameter
- From: "Andy Dyer" <adyer at righthandtech dot com>
- To: <ecos-discuss at ecos dot sourceware dot org>
- Date: Mon, 29 Mar 2004 09:49:07 -0600
- Subject: [ECOS] PCI spec Trhfa parameter
I notice that the PCI 2.3 spec requires a 2^25 clock
delay between deasserting reset on the bus and the first
configuration access (about 1 sec at 33 MHz clock). I
believe this is intended to allow devices like FPGAs
and cards with an embedded CPU to set themselves up.
It looks like none of the platform hals (of the ones I
looked at) take this parameter into account when setting
up the bus.
--
Andrew Dyer | adyer@righthandtech.com
Sr. Engineer | (630) 238-0789
RightHand Technologies | (630) 238-0469 (fax)
735 N. Edgewood Ave. |
Suite D |
Wood Dale, IL 60191-1261 |
USA |
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