[ECOS] ARM - re-enable IRQ exception

["Backhaus Willy" <w dot backhaus at newage-avkseg dot com>]

hello,

I'm trying to understand what the ARM IRQ-handling does.

I suppose, that the IRQ-exception for ARM is enabled (for first time after
reset), when the first thread context-switch happens. right?

if an IRQ exception occurs, the IRQ bit in the processor status register
remains set (means IRQ exceptions are disabled), until the corresponding ISR
was executed and before we want to call the pending DSR (if any). namely:


#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// Execute pending DSRs the interrupt stack
// Note: this can only be called from code running on a thread stack
FUNC_START_ARM(hal_interrupt_stack_call_pending_DSRs, r1)
        stmfd   sp!,{r4,r5,lr}
        // Disable interrupts
        mrs     r4,cpsr                 // disable IRQ's
        orr     r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE


////////////////////////////////////////////////////////////////////////////
/
////////////////// prepare cpsr with IRQ/FIQ enabled

        bic     r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
        msr     cpsr,r2
        // Switch to interrupt stack
        mov     r3,sp                   // save old stack pointer
        ldr     sp,.__interrupt_stack
        stmfd   sp!,{r3}                // stored at top of interrupt stack
        ldr     r2,.irq_level           // current number of nested
interrupts
        ldr     r3,[r2]
        add     r3,r3,#1                // bump nesting level
        str     r3,[r2]

////////////////////////////////////////////////////////////////////////////
/
///////////// here we will enable IRQ/FIQ for the first time after they
occur???

        msr     cpsr,r5                 // enable interrupts




thanks in advance.

regards,
Willy




-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss