This is the mail archive of the ecos-discuss@sources.redhat.com mailing list for the eCos project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: External I/O access on Adder


I cut TA pin and it's work.

Thanks

sugeng

On Sat, 05 Mar 2005 11:38:30 -0700, Gary Thomas <gary@mlbassoc.com> wrote:
> Please copy your replies to the mailing list so that all may benefit.
> Private support is only available under contract.
> 
> On Sun, 2005-03-06 at 00:50 +0700, Sugeng Widodo wrote:
> > On Sat, 05 Mar 2005 04:56:16 -0700, Gary Thomas <gary@mlbassoc.com> wrote:
> > > On Sat, 2005-03-05 at 09:38 +0700, Sugeng Widodo wrote:
> > > > Hi All,
> > > >
> > > > I have to access external chips with 13 bits address and 16 bits data.
> > > > I programmed OR4 and BR4 to use CS4 with address beetwen 0xFB000000 -
> > > > 0xFB007FFF and set the area to NOCACHE area. To do that I edited file
> > > > Adder.S and hal_aux.c.
> > >
> > > What were your exact changes?
> > >
> > > >
> > > > Lower half of the area is work fine , except I could not catch the CS4
> > > > with my logic analyzer ?? But the next half always make my apps crash
> > > > when I access it. Sometimes I could access it for 4 times and
> > > > sometimes it's crash when I accessed it on the first time.
> > > >
> > > > Anybody have any clue on that ?
> > >
> >
> > I add this on adder.S
> >         lwi     r3,0xFB000801
> >         lwi     r5,0xFFFF81F6
> >         stw     r5,OR4(r4)
> >         stw     r3,BR4(r4)
> >
> > and add this on hal_aux.c
> > CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
> >     // Mapping for the Adder 8xx development boards
> >     CYGARC_MEMDESC_CACHE(   0xfe000000, 0x00800000 ), // ROM region
> >     CYGARC_MEMDESC_NOCACHE( 0xff000000, 0x00100000 ), // MCP registers
> >     CYGARC_MEMDESC_NOCACHE( 0xfa000000, 0x00400000 ), // Control/Status+LEDs
> >     CYGARC_MEMDESC_NOCACHE( 0xfb000000, 0x00008000 ), // I ADD THIS LINE
> >     CYGARC_MEMDESC_CACHE(   CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE
> > ), // Main memory
> >
> >     CYGARC_MEMDESC_TABLE_END
> > };
> >
> > Is it enough or not ?
> 
> It looks right, but probably will not work as the 850 only has 4 TLB
> registers to use for the memory mapping and you've specified 5.
> Try merging the 0xfa and 0xfb segments like this:
>   CYGARC_MEMDESC_NOCACHE( 0xf8000000, 0x08000000 ),
> 
> --
> ------------------------------------------------------------
> Gary Thomas                 |  Consulting for the
> MLB Associates              |    Embedded world
> ------------------------------------------------------------
> 
> 


-- 
Sugeng Widodo
blog : http://elangmaya.blogspot.com

-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]