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Re: PowerPC FEC problems


On Fri, 2005-05-06 at 08:26 -0700, ken king wrote:
> --- Andrew Lunn <andrew@lunn.ch> wrote:
> > > > Check the addresses you are using from receive
> > and
> > > > transmit buffers.
> > > > Do you remember to map the virtual addresses
> > into
> > > > bus addresses before
> > > > programming them into the ethernet device? Does
> > > > memory realy exist at
> > > > the address? 
> > > > 
> > > >         Andrew
> > > > 
> > > > -- 
> > > > Before posting, please read the FAQ:
> > > > http://ecos.sourceware.org/fom/ecos
> > > > and search the list archive:
> > > > http://ecos.sourceware.org/ml/ecos-discuss
> > > > 
> > > Yes, I can dump memory around the BDs (Buffer
> > > descriptors) and they look correct. The memory
> > > pointed to by the BD can also be dumped and it
> > > has the same contents as displayed on the
> > > console if eth debugging is on, i.e looks like the
> > > bootp frames. I can put a scope on the PHYs
> > > tx_clock and tx_en -- the clock is running, but
> > > tx_en is never asserted.
> > 
> > You can look at the memory from the processor, so
> > you know you have
> > the correct virtual address. However, the DMA might
> > not be using the
> > virtual address. It will be using some bus address.
> > Bus addresses can
> > be different from virtual addresses. Read the
> > datasheet and see what
> > it says about the addresses to be used for
> > programming the DMA engine.
> > 
> >         Andrew
> I thought that the MMU was off -- the config tool has
> it grayed out. However the MMU is on. Just for fun, I
> disabled it. It would appear that physical addr =
> virtual addr. I still get the bus error after
> verifying the MMU is disabled before and after. I also
> checked that the BDs are correct before and after.
> 

Correct.  The MMU has to be on for this processor in order to
provide proper cache control.  It should be mapped 1-1, so there
is no difference in addresses that the CPU sees vs what the CPM
(FEC) sees.

> As for the data book, it doesnt say much about the
> FEC DMA  it seems to imply that it is different from
> the SDMA which got its own section.

The FEC is its own beast - it does not use any other DMA engine.

Make sure that your Tx buffer descriptor ring is correct and has
been fully initialized.  When you execute the fec->TxUpdate=1
instruction, that tells the FEC to scan for work.

Have you done anything special to your port or the driver?  This
code is known to work on a number of CPUs, including the 852T.


-- 
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------


-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
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