//===========================================================================
//
// RAM startup linker control script
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================

MEMORY
{
    //rom (rx)        : ORIGIN = 0x00F00000, LENGTH = 0x00100000
    //ram (wx)        : ORIGIN = 0x00100000, LENGTH = 0x00D00000
	rom(rx)	      : ORIGIN = 0xffe00000, LENGTH = 0x00100000
	ram(wx)	  	  : ORIGIN = 0x00000000, LENGTH = 0x01000000
}

SECTIONS
{
    
    SECTIONS_BEGIN
    GENERIC_SECTION				(romvec, rom,0xffe00000 , LMA_EQ_VMA, 0x400)
    SECTION_text                (rom, ALIGN (0x4), FOLLOWING (.romvec))
    SECTION_fini                (rom, ALIGN (0x4), FOLLOWING (.text))
    SECTION_rodata1             (rom, ALIGN (0x4), FOLLOWING (.fini))
    SECTION_rodata              (rom, ALIGN (0x4), FOLLOWING (.rodata1))
    SECTION_fixup               (rom, ALIGN (0x4), FOLLOWING (.rodata))

    //   WARNING: If you change the order of these sections, be sure to change
    // the location of the data section.

    SECTION_gcc_except_table    (rom, ALIGN (0x4), FOLLOWING (.fixup))
    __rom_data_addr = ABSOLUTE(.);

    GENERIC_SECTION             (ramvec, ram,0, LMA_EQ_VMA, 0x400)
    SECTION_data                (ram, ALIGN (0x4), FOLLOWING (.ramvec), __rom_data_addr)
    SECTION_sbss                (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA)
    SECTION_bss                 (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA)
    SECTION_uninvar             (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA)

    // Allocate a heap section.

    SECTION_heap1               (ram, ALIGN (0x4), LMA_EQ_VMA, 0x10000)
    // The build tool looks for this "CYG_LABEL_DEFN..." string.
    CYG_LABEL_DEFN(__heap1) = ABSOLUTE (__heap1_start);

    SECTIONS_END
}

hal_virtual_vector_table = 0xE00000;