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Re: Re: DSR Scheduling Problem
daniel.neri@sigicom.se (Daniel NÃri) writes:
> Grant Edwards <grante@visi.com> writes:
>
> > On 2006-01-14, Paul D. DeRocco <pderocco@ix.netcom.com> wrote:
> >
> >> If the transmitter has a hardware FIFO, and the software
> >> transmits one byte per interrupt,
> >
> > Then the sofware is completely and utterly broken. It doesn't
> > deserve to work.
> >
> >> then presenting a block of data to it after an idle period
> >> will invoke the ISR/DSR a slew of times until the FIFO is
> >> full.
> >
> > That's insane. Nobody with a clue would write software like that.
>
> Actually, the generic 16x5x serial driver in eCos works exactly like
> that.
Actually, it doesn't.
>
> > When you get a TX interrupt you write data to the tx FIFO until it's
> > full.
>
> Yep. I've made a somewhat quick-and-dirty fix that is attached below.
This already happens. pc_serial_putc() returns true or false,
depending on whether it transmitted the byte. In the 16550 this means
that it will only return false when the FIFO fills up. The generic
serial code calls the putc() driver routine in a loop to transmit
bytes until it returns false.
--
Nick Garnett eCos Kernel Architect
http://www.ecoscentric.com The eCos and RedBoot experts
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