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Re: Re: DSR Scheduling Problem


Hi,

I've added a DSR FIFO option which works like the LIST version, but in FIFO order. I've tested it for some time now and it works will. Please give it a try.

A doubt about the names:


+#ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_FIFO
+
+Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list[CYGNUM_KERNEL_CPU_MAX];
+Cyg_Interrupt* volatile Cyg_Interrupt::last_dsr[CYGNUM_KERNEL_CPU_MAX];
+
+#endif
+

To be consistent with array implementation, isn't it better to call the
above variables "dsr_list_head" and "dsr_list_tail", respectively?

Yes, no problem. It's just a (working) suggestion for the implementation.


Bye...

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