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Re: Bus space vs PCI space vs CPU space


On Wed, Feb 15, 2006 at 09:45:56PM -0800, Chuck McManis wrote:
> Another evening, another confusment as my daughter would say.
> 
> So a few of the ethernet drivers (including the old Rhine driver) define a 
> macro HAL_PCI_CPU_TO_BUS. The purpose of which is to map virtual addresses 
> into physical addresses to pass to the chip. However in eCos on the x86 HAL 
> that macro maps to basically (x) because there is a 1:1 relationship 
> between physical and virtual addresses.
> 
> So here is the question, "Do you care?" or more specifically this driver 
> I'm working on will be available to the eCos community at large but it is 
> targeted at a very specific piece of hardware that pretty much only runs on 
> a x86 system (unlike the Rhine driver which can run on different kinds of 
> systems). So I'm wondering how much time and effort I should spend after 
> this thing is running the way I need it to work on things like endianess 
> and bus space macros, neither of which are an issue in the chips 'native' 
> environment.

This ethernet is inside a VIA South bridge? 

So VIA basically have an Ethernet ASIC core macro which they have put
into this south bridge. The questions you need to ask are, have VIA
also used this ethernet core in any other chips, or could they
potentially use it in any other chips which are radically different,
ie not i386 south bridges. 

What would happen eg if they made a south bridge for a AMD64, or a 64
bit intel processor? Actually, this is probably not that interest
since nobody has yet run eCos on 64 bit machines running in 64 bit
mode. So there is more to worry about than just the ethernet driver.

Do VIA make chipsets for none i386 architectures? 

Do VIA make standalone ethernet chipsets?

        Andrew

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