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Re: Hard-Realtime behaviour



Sorry for not replying for a few days.



In my earlier query about pipeline I was not worried about that level of detail except that it might hinder the task of detecting if a particular task is deterministic.



Now I am actually listing all the kernel primitives and the no. of clock-cycles it takes to execute the primitives. How can I do that. I am working on an i386 (Merlin - 25 MHz. Hence no rdtsc() ).



Then based upon the latencies of the kernel primitives, we would select primitives and make them more deterministic.



This I think would be the first step in making eCos "Hard Real-Time".
Also please advise if integration of timing attributes of a process into the thread_creation API and implicit timers/alarms creation necessary. Because this is what RTAI does. Is this necessary.



Functions necessary to make eCos "Hard" realtime:


@Memory Management:
--------------------

Recently read an O(1) implmentation for malloc and free. This was developed as part of OCERA project. Accoording to the authors of the paper, it performs just like Douglas Lea allocator but performance does not degrade with large blocks. Would be future work.


@Turning Cache on/off : -----------------------

We can turn of caches when we want "hard" realtime. This option already exists in eCos.


@DMA transfers: ---------------

This is hardware dependent, although for my project we do not have a hard-disk.


@Interrupt Handling : ---------------------

I am not fully aware of interrupt handling in eCos. Can some-one explain eCos's interrupt handling w.r.t the mail from Mr. Wolfgang on 29th May.


@Integrating timing attributes of a process with the scheduler : ---------------------------------------------------------------

This is what I am asking for advise in this mail.


@IPC with priority invesion and priority inheritance : ------------------------------------------------------

Already exists.


@Realtime TCP/IP stack : ------------------------

To be done. But I am only interested in non-network related programs currently.




Can others please reply if I am missing some area that might hinder in making eCos "hard" real-time OS.





On Tue, 30 May 2006, Andrew Lunn wrote:


On Tue, May 30, 2006 at 02:36:05PM +0530, R Vamshi Krishna wrote:

Continuing on the discussion, doesn't pipelining on modern processors add to our woes. Because then we cannot really determine if a particular instruction is going to 'x' cycles or 'y' cycles.

Realy you need to talk to the silicon vendor, or at least read the data sheet and see what it says.

However I think pipelining in itself should not be a problem.  It
should be deterministic under normal conditions. Only when things go
wrong will it be none deterministic, ie interrupts, exceptions, cache
misses is you have caches enabled.

If you are on a processor with HT like technology then i expect the
pipeline becomes none deterministic unless you disable all other
"processors".

Really, if you are worried about this level of detail, you probably
should be using a Z80, or some similar level of processor technology,
where you know what it is doing.

Andrew


-- Regards, Vamshi

-------------------------------------------------
R.Vamshi Krishna,
M.Tech. CSE (II year),
IIT Bombay
Room no. 320, A-wing, Hostel-12
Mobile : +919869781633
-------------------------------------------------

Yesterday is a past, tomorrow is a future , today is a gift that's why it's called 'present'

--
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