Re: [ECOS] Thumb support for arm9 variants?

[Andrew Lunn <andrew at lunn dot ch>]

On Mon, Jun 12, 2006 at 10:02:57PM +0200, Lars Povlsen wrote:
> 
> Hello All!
> 
> I have been tinkering with a couple of ARM9/ARM926 platforms for which I
> have built an eCos HAL modeled after the ARM9 variants in
> packages/hal/arm/arm9/*. Everything (mostly) is looking great, but
> wanting to test the thumb-mode of my chips turned out to be less than
> straight-forward...
> 
> I deduced that I was unable to just "enable" in configtool due to
> missing "implements CYGINT_HAL_ARM_THUMB_ARCH". But with that added (and
> the -mthumb compile options that goes along), it seems that not all code
> in hal/arm/arm9 is "thumb"-compatible:
> 
> arm-elf-gcc -c
> -I/proj/sw/usr/lpovlsen/ecos/build_luton28_ram/install/include
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/sr
> c
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/te
> sts -I.
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/sr
> c/ -finline-limit=7000 -mthumb -mthumb-interwork -mcpu=arm9 -Wall
> -Wpointer-arith -Wstrict-prototypes -Winline -Wundef  -g -O2
> -ffunction-sections -fdata-sections  -fno-exceptions
> -Wp,-MD,src/arm9_misc.tmp -o src/hal_arm_arm9_var_arm9_misc.o
> /users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/src/
> arm9_misc.c
> /tmp/ccmyIUwO.s: Assembler messages:
> /tmp/ccmyIUwO.s:24: Error: bad instruction `mrc p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:24: Error: register expected, not '#0x000F' -- `orr
> r1,r1,#0x000F'
> /tmp/ccmyIUwO.s:24: Error: bad instruction `mcr p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:26: Error: bad instruction `mrc p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:26: Error: register expected, not '#0x1000' -- `orr
> r1,r1,#0x1000'
> /tmp/ccmyIUwO.s:26: Error: register expected, not '#0x0002' -- `orr
> r1,r1,#0x0002'
> /tmp/ccmyIUwO.s:26: Error: bad instruction `mcr p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mrs r1,cpsr'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x1F' -- `bic
> r1,r1,#0x1F'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x13' -- `orr
> r1,r1,#0x13'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `msr cpsr,r1'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c7,c7,0'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c7,c10,4'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c8,c7,0'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mrc p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x1000' -- `bic
> r1,r1,#0x1000'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x0007' -- `bic
> r1,r1,#0x0007'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c1,c0,0'
> make[1]: *** [src/arm9_misc.o.d] Error 1 

Where did these fragments of assembly code come from?  I would not
expect the compiler to generate ARM code when it is supposed to be
generating thumb code. So is this some inline assembly? eg is this
cache manipulation? You might need to write thumb equivelents.

      Andrew

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