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Re: problem enabling the caches on powerpc
- From: Gary Thomas <gary at mlbassoc dot com>
- To: saurabh prakash <saurabhp75 at gmail dot com>
- Cc: ecos-discuss <ecos-discuss at ecos dot sourceware dot org>
- Date: Thu, 29 Jun 2006 04:56:56 -0600
- Subject: Re: [ECOS] problem enabling the caches on powerpc
- References: <eafe42230606282250k7dcbc7c1k8bc95507a97c5c41@mail.gmail.com>
saurabh prakash wrote:
hi,
i am working on mbx type board, with mpc860P, i had successfully worked on
similar board in the past. but i am having problems enabling the
caches on the current
board. As soon as the macro HAL_ICACHE_ENABLE() executes, the cpu
gives an exception(SEI). To be precise the second "isync" gives an
exception. I have modified the
HAL_ICACHE_SIZE, HAL_ICACHE_LINE_SIZE, HAL_ICACHE_WAYS.... etc according to
the variant i am using but without any results. Can anybody suggest
any solution.
#define HAL_ICACHE_ENABLE()
asm volatile ("isync;"
"mtspr %0, %1;"
"isync" <----- Executing this gives an exception
: : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
The most likely cause is your hardware timings, in particular DRAM
setups. When you enable the cache(s), the CPU will start using burst
access to memory. If you've not set this up properly, exceptions will
occur.
Check your UPM tables.
--
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Gary Thomas | Consulting for the
MLB Associates | Embedded world
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