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Re: asymmetric block size in Strata P30/P33 flash


Jacob Avraham wrote:
Jacob Avraham wrote:
Hi,

I'm about to bringup an IXP420-based board with a Strata P33 flash
on
it.
I'm using Redboot 2.02.

BTW - this number means nothing to us - it's an artifact of getting your code from Intel.

I wonder if Redboot can handle the fact that this chip has 2 erase
block
sizes:
128k and 32k. I saw in the code that there is one variable for the
block
size,
so it makes me suspicious...
This is handled by mapping the 32K blocks onto a 128K block.
Look at how the AMD drivers handle it.

I don't see the infrastructure for this in the starta code, which uses
CFI query to get the block size.
Are you suggesting to modify the strata driver to support sub-blocks?

No, I'd clone it to make a whole new class of devices and add this additional support.

You might also look at the latest [anon CVS] tree, just to make
sure you're not reinventing the wheel!

--
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------

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