[ECOS] POSIX & SMP compatibility and other problems in a Leon3 platform

["Iñigo Barrera" <inigoku at gmail dot com>]

Hi,

I am using eCos on a Leon3-based SMP system, with a modified interrupt
controller, so that I had to adapt the interrupt and SMP-related HAL
functions. I am also using the POSIX compatibility layer on top.

 I am running into several problems, and before digging too much
(more) into the kernel code, I'd like to ask some questions to the
mailing list, in case someone has already run into them before (sorry
if they seem random, I'm trying to gather everything into a single
e-mail):

1) I am running into a lot of problems when using the POSIX timers
with the real system, mainly deadlocks related to timer list
corruption or scheduler lock going out of sync. This didn't use to
happen in the simulations, but with the real system (and the real
timings) it's happening all the time. Though it all might be related
to the new interrupt controller implementation, I just wanted to ask
if someone has used the POSIX layer (specifically timers) on a SMP
platform (specifically a Sparc or Leon platform), and whether there
were some problems or issues I should be aware of.

2) with the new interrupt controller, several SMP (CPU communication)
interrupts can get grouped, and I have found that I had to prevent
consecutive calls to "reschedule" and "timeslice" inside the same DSR,
otherwise the thread list got corrupted. Is that normal? Or should it
work, and it's a sympthom of other (maybe timing-related) problem?

3) to be able to use a big number of interrupts, they are grouped into
interrupt banks, and I need to decode the real interrupt inside the
ISR, and post the DSR for the decoded interrupt. This is maybe a basic
question, but can I post the DSR inside the ISR, or do I need to
remember the correct DSR and do it in the interrupt_end() function? In
another words, is it necessary to lock the scheduler before posting
the DSR? (I have tried both implementations and I can't see any
difference apart from timing itself).

4) has someone adapted eCos for Leon3 to a "slow" interrupt controller
(explicit acknowledge, CPU message destination selection by masking),
than can share the experience, like timer or SMP CPU message interrupt
adaptation, or workarounds for the different timing misadjustments?

Thank you very much in advance for your help,
Inigo.

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