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Re: Changing PLL register was: Configuration for at91sam7se-ek
- From: Andrew Lunn <andrew at lunn dot ch>
- To: "Davies, Greg" <Greg dot Davies at Ultra-UEMS dot com>
- Cc: ecos discuss <ecos-discuss at ecos dot sourceware dot org>
- Date: Tue, 17 Jun 2008 15:20:00 +0200
- Subject: Re: [ECOS] Changing PLL register was: Configuration for at91sam7se-ek
- References: <A25DBA3B0717824BAFD61F81242D5DBDCF1572@exchange.Ultra-UEMS.ca> <A25DBA3B0717824BAFD61F81242D5DBDE1A492@exchange.Ultra-UEMS.ca> <A25DBA3B0717824BAFD61F81242D5DBD01578D0B@exchange.Ultra-UEMS.ca> <A25DBA3B0717824BAFD61F81242D5DBD01578DE7@exchange.Ultra-UEMS.ca>
On Tue, Jun 17, 2008 at 08:50:50AM -0300, Davies, Greg wrote:
> I've found the cause of all the strange problems I've had
> that I asked you guys for help with, and I want to share,
> mostly for newbies (like myself) to find in the archives.
> This includes all my issues in the "Changing flash wait state
> on SAM7" thread.
>
> The cause of all of it was that there was no PLL filter.
Hi Greg
It is good to here you got your system working.
Im not really a HW engineer, so maybe this is a dumb question...
The Atmel document doc6112.pdf, which is the reference design of the
AT91SAM7S, where you missing the two capaciters to ground on either
side of the crystal? Or the resister/capacitor network to PLLRC? I
guess the second?
Thanks
Andrew
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